Exclusive-OR 최소화 기법에 의한 다치논리 함수의 구성 및 실현 ( A Constructing Theory of Multiple-Valued Logic Functions based on the Exclusive-OR Minimization Technique and Its Implementation )

박동영 ,  김흥수

전자공학회논문지-B

1992 .11

A Visual-Based Logic Minimization Method

Eungi Kim

한국산업정보학회논문지

2011 .12

M-AND , M-OR , NOT 연산을 이용한 다치 논리함수의 간단화에 관한 연구 ( A Study on Minimization of Multiple-Valued Logic Functions using M-AND , M-OR and NOT Operators )

송홍복 ,  김영진 ,  김명기

한국통신학회논문지

1992 .06

PLA 설계를 위한 논리함수 최소화 기법 ( A Logic Function Minimization Technique for programmable Logic Array Design )

이재민 ,  신용철 ,  임인칠

대한전자공학회 학술대회

1985 .01

기호다치논리를 이용한 Fuzzy Rule Minimization에 관한 연구

김명순

한국컴퓨터정보학회논문지

1999 .12

A Study on the Circuit Minimization Technique Using Edge Multiple-Valued Decision Diagrams

Sung Il Han ,  Jong Hak Hwang ,  Boo Sik Shin 외 3명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1997 .01

PLA 설계용 논리 최소화 알고리즘 ( Fast Logic Minimization Algorithm for Programmable Logic Array Design )

최상호 ,  한석붕 ,  임인칠

대한전자공학회 학술대회

1983 .01

Implementation of Logic Simulator

Gi Han Ryu ,  Hwan Seog Kim ,  Cheon Hee Yi

International Conference on Electronics, Informations and Communications

1991 .01

Implementation of logic simulator

Gi-Han Ryu ,  Hwan-Seog Kim ,  Cheon-Hee Yi

ICEIC : International Conference on Electronics, Informations and Communications

1991 .08

Homography Estimation with L_∞ Norm Minimization Method

Hyunjung LEE ,  Yongduek SEO ,  Richa 외 2명

대한전자공학회 기타 간행물

2008 .01

Method of Logic Function Multi-Level Speed-Independent Implementation

Igo ,  Lembe ,  ski 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2005 .07

PLA 설계용 고속 논리최소화 알고리즘 ( Fast Logic Minimization Algorithm for Programmable-Logic-Array Design )

최상호 ,  임인칠

전자공학회지

1985 .03

Medical Image Restoration Using L1-Minimization

D M Bappy ,  Insu Jeon

대한기계학회 춘추학술대회

2015 .05

A Logic Minimization Approach to MUX-based FPGA Technology Mapping

Jae Bum Kim ,  Chu Shik Jhon

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1996 .01

A POWER MINIMIZATION TECHNIQUE IN A 54 x 54 BIT MULTIPLIER

Min Kyu Song ,  Kunihi ,  o Asada

ICVC : International Conference on VLSI and CAD

1995 .01

Multiple-Valued Logics and Classification Criteria

Václav Pinkava

한국지능시스템학회 논문지

1993 .03

LOGIC-CHECKER : A CORRECTING FUNCTION FOR GATE ERRORS IN LOGIC SIMULATION AND ITS IMPLEMENTATION

Satoshi Wakabayashi ,  Hi ,  oyuki Ishikawa 외 1명

JTC-CSCC : Joint Technical Conference on Circuits Systems, Computers and Communications

1989 .01

순서 집합 개념을 이용한 새로운 논리 최소화 알고리즘 ( A Logic Minimization Algorithm Using the Concept of Ordering Set )

백영석 ,  이성봉 ,  김승연 외 1명

대한전자공학회 학술대회

1986 .01

A Modular Function Decomposition on Multiple-Valued Logic

Jai Sock Choi ,  Jong Oh Kim ,  Hong Bok Song 외 2명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1997 .01

3-VALUED 논리함수의 MINIMIZATION에 관한 연구

임인칠 ,  이근만

대한전자공학회 학술대회

1980 .01