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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.11 No.1
- 발행연도
- 2011.3
- 수록면
- 33 - 39 (7page)
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초록· 키워드
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H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED ARCHITECTURE
Ⅲ. DESIGN OF H.264 DECODER
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (14)
참고문헌 신청
1. [보고서] - Joint Video Team / 2003 / Draft ITU-T Recommendation and Final Draft International Standard of Joint Video Specification
2. [학술대회논문] - C.-Y. Tsai / 2005 / Bandwidth Optimized Motion Compensation Hardware Design for H.264/AVC HDTV Decoder / Proceedings of 48th Midwest Symposium on Circuits and Systems : 1199 ~ 1202
3. [학술대회논문] - M. Alle / 2007 / High performance VLSI implementation for H.264 Inter/Intra prediction / Proceedings of IEEE International Conference on Comsumer Electonics : 1 ~ 2
4. [학술대회논문] - W.-N. Lie / 2005 / Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding / Proceedings of IEEE International Symposium on Circuits and Systems : 23 ~ 26
6. [학술대회논문] - C. Lee / 2010 / Design of an H.264 Decoder with Variable Pipeline and Smart Bus Arbiter / Proceedings of 2010 International SoC Design Conference : 432 ~ 435
2. [학술대회논문] - C.-Y. Tsai / 2005 / Bandwidth Optimized Motion Compensation Hardware Design for H.264/AVC HDTV Decoder / Proceedings of 48th Midwest Symposium on Circuits and Systems : 1199 ~ 1202
3. [학술대회논문] - M. Alle / 2007 / High performance VLSI implementation for H.264 Inter/Intra prediction / Proceedings of IEEE International Conference on Comsumer Electonics : 1 ~ 2
4. [학술대회논문] - W.-N. Lie / 2005 / Hardware-efficient computing architecture for motion compensation interpolation in H.264 video coding / Proceedings of IEEE International Symposium on Circuits and Systems : 23 ~ 26
6. [학술대회논문] - C. Lee / 2010 / Design of an H.264 Decoder with Variable Pipeline and Smart Bus Arbiter / Proceedings of 2010 International SoC Design Conference : 432 ~ 435
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