지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.5
- 수록면
- 2,438 - 2,445 (8page)
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초록· 키워드
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Different optimization techniques have been proposed for Phase Lock Loops (PLLs) in power system applications. A comparative study, accomplished through simulations for different optimization techniques, is presented here. Loop controllers are critical in determining the transient response of the PLL. Trade-off’s in designing loop controllers for power system applications are discussed here. Extensive simulation results are presented for different optimization techniques including using periodic notch filter which shows better performance when compared with other existing approaches. The results are summarized in a table which helps in selecting the appropriate PLL optimization technique.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. CLASSICAL PLL
Ⅲ. LAG/LEAD CONTROLLER
Ⅳ. PI CONTROLLER
Ⅴ. PI AND NOTCH CONTROLLER
Ⅵ. PI AND MA CONTROLLER
Ⅶ. PI AND HPF CONTROLLER
Ⅷ. PROPOSED PI AND PNOTCH CONTROLLER
Ⅸ. SINGLE PHASE SCHEMES HAVING EXTRA FILTERS IN THE LOOP
Ⅹ. PI AND PNOTCH PREFILTER
XI. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-560-000302189