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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2011.10
- 수록면
- 1,275 - 1,286 (12page)
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초록· 키워드
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This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.
목차
ABSTRACT
1. INTRODUCTION
2. FULL SEARCH BLOCK MATCHING ALGORITHM
3. DESIGN OF SYSTOLIC ARRAY
4. RESULTS and DISCUSSION
5. CONCLUSION
REFERECNES
참고문헌 (15)
참고문헌 신청
J. L. Mitchell / 1996 / MPEG video compression standard / Chapman and Hall
S. Zhu / 2000 / A New Diamond Search Algorithm for Fast Block-Matching Mostion Estimation / IEEE Trans. on Image Processing 9(2):287~290
S. Y. Kung / 1988 / VLSI array processors / Prentice Hall
Y. Huang / 2006 / Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results / Journal of VLSI Signal Processing 42:297~320
T. Komarek / 1989 / Array Architecture for Block Matching Algorithms / IEEE Trans. on Circuits and Systems 36(10):1301~1308
S. Zhu / 2000 / A New Diamond Search Algorithm for Fast Block-Matching Mostion Estimation / IEEE Trans. on Image Processing 9(2):287~290
S. Y. Kung / 1988 / VLSI array processors / Prentice Hall
Y. Huang / 2006 / Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results / Journal of VLSI Signal Processing 42:297~320
T. Komarek / 1989 / Array Architecture for Block Matching Algorithms / IEEE Trans. on Circuits and Systems 36(10):1301~1308
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UCI(KEPA) : I410-ECN-0101-2013-004-001292010