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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 24 - 27 (4page)
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초록· 키워드
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In this paper, we propose delay-compensation techniques for ultra-low power subthreshold digital circuits and a nano-ampere CMOS current reference circuit that is tolerant to threshold voltage variations. Delay in digital circuits that are operated in the subthreshold region of a MOSFET changes exponentially with variations in threshold voltage. Therefore, compensation techniques are required to mitigate the variation. To achieve robust operation for extremely low voltage digital circuits, threshold-voltage monitoring and supply-voltage scaling techniques are developed. By monitoring the threshold voltage of each LSI chip and exploiting the voltage to supply voltage to subthreshold digital circuits, variations in delay time can be suppressed significantly. Monte Carlo SPICE simulation demonstrates that delay-time distribution can be improved from lognormal to normal. The coefficient of variation for the proposed technique is 31%.
목차
Abstract
I. INTRODUCTION
II. DELAY COMPENSATION
III. CURRENT REFERENCE
IV. CONCLUSION
ACKNOWLEDGMENT
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001474303