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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 112 - 115 (4page)
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초록· 키워드
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This paper presents the design considerations of electrostatic discharge (ESD) protection for RF system-on-chip (SOC) in advanced CMOS technology. Different RF ESD protection strategies and circuit topologies are reviewed and discussed. The low-noise amplifiers (LNAs), often directly explored under the risk of ESD in wireless communication chips, are co-designed with the ESD blocks. By treating the ESD devices as a part of the input matching network, we demonstrate RF LNAs with excellent ESD protection, while the RF characteristics are almost unaffected. Using the proposed RF junction varactors for ESD design, a V-band LNA in 65 nm CMOS with a noise figure of 5.2 dB and a power gain of 10.9 dB presents a ESD protection level up to 4.0 KV, and also with the CDM ESD protection up to 8.7 A.
목차
Abstract
I. INTRODUCTION
II. ESD PROTECTION DESIGN FOR RF CIRCUITS
III. V-BAND LNA CO-DESIGNED WITH ESD PROTECTION
IV. CONCLUSION
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UCI(KEPA) : I410-ECN-0101-2013-569-001474525