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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2011.11
- 수록면
- 436 - 439 (4page)
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초록· 키워드
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Application-specific instruction processor is a new design methodology to develop optimized processors for specific applications. This paper proposes a new application-specific instruction processor and compiler for multi-standard video decoding. They are based on the 6-stage pipelined dual issue VLIW+SIMD architecture, efficient instructions for multistandard video decoding, and compiler mapping techniques such as CKF(compiler known function) and inline assembly. SMIC 130nm process is used for implementation of the proposed architecture whose approximate gate count is about 130K and runs at 125MHz. Compared to the existing ARM processor, the proposed architecture and compiler result in about 20% improvement in video decoding in terms of total cycles as well as smaller hardware complexity.
목차
Abstract
I. INTRODUCTION
II. APPLICATION SPECIFIC PROCESSOR AND COMPILER
III. IMPLEMENTATION AND EXPEMENTAL RESULTS
IV. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001475320