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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2009.11
- 수록면
- 295 - 300 (6page)
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초록· 키워드
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After a design has been implemented in silicon, it is immensely difficult to debug any functional or silicon related problems. Hence, anything that can be done up-front at the RTL or gate-level to prevent errors will be extremely beneficial. So far, simulation-based dynamic verification has been relied upon heavily to verify the functionality of designs. In this paper, we summarize a number of static verification technologies ? from simple RTL lint to sophisticated formal property verification ?that can complement dynamic verification. These technologies can also help with low power verification and static timing analysis. Most importantly, they can target silicon related problems ? such as clock domain crossing uncertainties, Xstates, and uninitialized registers ? that cannot be verified with dynamic simulation.
목차
Abstract
I. INTRODUCTION
II. STATIC DESIGN ANALYSIS
III. USAGE OF ASSERTIONS
IV. STATIC VERIFICATION TECHNOLOGIES
V. USAGE REQUIREMENTS
VI. RESULTS
VII. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2013-569-001482832