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논문 기본 정보

자료유형
학술저널
저자정보
Bor-Ren Lin (National Yunlin University) Huann-Keng Chiang (National Yunlin University) Chih-Yuan Cheng (National Yunlin University)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.12 No.2
발행연도
2012.3
수록면
249 - 257 (9page)

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초록· 키워드

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An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. CIRCUIT CONFIGURATION
Ⅲ. OPERATION PRINCIPLE
Ⅳ. CIRCUIT ANALYSIS
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSION
ACKNOWLEDGMENT
REFERENCES

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