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논문 기본 정보

자료유형
학술저널
저자정보
Jing Li (University of Electronic Science and Technology) Ning Ning (University of Electronic Science and Technology) Ling Du (University of Electronic Science and Technology) Qi Yu (University of Electronic Science and Technology) Yang Liu (University of Electronic Science and Technology)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.1
발행연도
2012.3
수록면
99 - 106 (8page)

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초록· 키워드

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For CMOS technology of 65 nm and beyond, the gate leakage current can not be negligible anymore. In this paper, the impact of the gate leakage current in ring voltage-controlled oscillator (VCO) on phaselocked loop (PLL) is analyzed and modeled. A voltage-to-voltage (V-to-V) circuit is proposed to reduce the voltage ripple on Vctrl induced by the gate leakage current. The side effects induced by the V-to-V circuit are described and optimized either. The PLL design is based on a standard 65 ㎚ CMOS technology with a 1.8 V power supply. Simulation results show that 97 % ripple voltage is smoothed at 216 ㎒ output frequency. The RMS and peak-to-peak jitter are 3 ps and 14.8 ps, respectively

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. GATE LEAKAGE CURRENT MODELING AND OPTIMIZATION
Ⅲ. SIMULATION RESULTS
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES

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UCI(KEPA) : I410-ECN-0101-2013-569-001723116