지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국정보기술학회 JOURNAL OF ADVANCED INFORMATION TECHNOLOGY AND CONVERGENCE JOURNAL OF ADVANCED INFORMATION TECHNOLOGY AND CONVERGENCE, VOL. 2, NO. 1
- 발행연도
- 2012.7
- 수록면
- 15 - 21 (7page)
- DOI
- 10.14801/JAITC.2012.2.1.15
이용수
초록· 키워드
오류제보하기
Satisfaction has been found only in research on standard connection method to meet the requirements of SoC design for the past 10 years. But number of core inside SoC may come to exceed 100 because less than 65nm of design method have led to being used according to development of chip integration technology, and expansion of function. And now communication between chip cores entered on a new phase that characteristics of network should be understood by going over simple bus basis. Characteristics of network like this may include receiving socket at the terminal of network to permit independence to cores, and expandability that network may be expanded or reduced at need, as well as standard interface protocol. NoC technology provides on-chip network arranged in a row, by using packet protocol through a series of routers. On the other hand, research on artificial neural network for implementation of human intellectual power with digital technology has continued for a long time, but the research was delayed because of complexity that it should be composed of matrix of numerous processing element (PE). Therefore if digital neural network is designed on the basis of NoC, communication load between PEs, and execution time will be decreased, and design of low power will be possible. And various architecture of digital neural network can be implemented because recomposition and modification of digital neural network is easy.
목차
Abstract
1. Introduction
2. Digital neural network architecture
3. Design of NoC Digital Neural Network
4. Conclusion
References
참고문헌 (10)
참고문헌 신청
W. Cho / 1986 / Study on the Design of Arithmetic Processors Using Residue Number System
Y. Jung / 1992 / A Study On The Arithmetic Circuit Design of Sigmoid Function Generator in Digital Neural Network
H. Yoon / 1991 / A Study on the Design of Array Processor for Digital Neural Network / Proc. Workshop on AI, Neural Network and Fuzzy System
H. Yoon / 1993 / An Implementation Of Digital Neural Network Using Systolic Array Processor / Journal of The Institute of Electronics Engineers of Korea 30-B(2)
Hyun-sik Yoon / 1994 / Design of High Speed Digital Neural Network Using Residue Number System
Y. Jung / 1992 / A Study On The Arithmetic Circuit Design of Sigmoid Function Generator in Digital Neural Network
H. Yoon / 1991 / A Study on the Design of Array Processor for Digital Neural Network / Proc. Workshop on AI, Neural Network and Fuzzy System
H. Yoon / 1993 / An Implementation Of Digital Neural Network Using Systolic Array Processor / Journal of The Institute of Electronics Engineers of Korea 30-B(2)
Hyun-sik Yoon / 1994 / Design of High Speed Digital Neural Network Using Residue Number System
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