지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 947 - 953 (7page)
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초록· 키워드
오류제보하기
The latch-up immunity of the high voltage power clamps used in high voltage ESD protection devices is very becoming important in high-voltage applications. In this paper, a stacking structure with a high holding voltage and a high failure current is proposed and successfully verified in 0.18um CMOS and 0.35um BCD technology to achieve the desired holding voltage and the acceptable failure current. The experimental results show that the holding voltage of the stacking structure can be larger than the operation voltage of high-voltage applications. Changes in the characteristics of the stacking structure under high temperature conditions (300K-500K) are also investigated.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. SINGLE SCR-BASED ESD PROTECTION DEVICE WITH A HIGH HOLDING VOLTAGE
Ⅲ. STACKED SCR-BASED ESD PROTECTION DEVICE
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENT
REFERENCES
참고문헌 (7)
참고문헌 신청
J. B. Huang / 2001 / ESD protection design for advanced CMOS / Proc. SPIE :123~131
Young Chung / 2006 / Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS / Reliability Physics Symposium :352~355
V. Vashchenko / 2004 / High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps / IEEE Transactions on Devices and Materials Reliability 4:273~280
M. D Ker / 1999 / How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on / Journal of Electro- statics 47:215~248
Y. Koo / 2009 / Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology / Microelectronics Journal 40:1007~1012
Young Chung / 2006 / Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS / Reliability Physics Symposium :352~355
V. Vashchenko / 2004 / High holding voltage cascoded LVTSCR structures for 5.5-V tolerant ESD protection clamps / IEEE Transactions on Devices and Materials Reliability 4:273~280
M. D Ker / 1999 / How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on / Journal of Electro- statics 47:215~248
Y. Koo / 2009 / Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology / Microelectronics Journal 40:1007~1012
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UCI(KEPA) : I410-ECN-0101-2014-560-000995673