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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 195 - 198 (4page)
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초록· 키워드
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This paper presents a new charge recovery logic structure called Complementary Pass-transistor Boost Logic (CPBL). CPBL is a low-power charge recovery logic structure powered by 2-phase non-overlap alternating power clocks and requires no DC power supply. To demonstrate the energy efficiency of CPBL, 4-bit counter is designed to show the energy comparison among CPBL, Complementary Pass-transistor Adiabatic Logic (CPAL) and the conventional static CMOS with 0.18 ㎛ process. The simulation results indicate that CPBL implementation reduces about 65% power dissipation compared with the static CMOS counterpart in a range from 50㎒ to 500㎒ and dissipates about 40% energy with respect to CPAL at 200㎒.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. COMPLEMENTARY PASS-TRANSISTOR BOOST LOGIC
Ⅲ. 4-BIT COUNTER SIMULATION AND COMPARISON
Ⅳ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000729490