지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2012.11
- 수록면
- 353 - 356 (4page)
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초록· 키워드
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The SOC verification is challenging in verifying multiple IPs’ integration and on-chip inter-IP communication in the complex system. SOC Engineers have to spend tremendous efforts on learning details inside IP design, developing complex testbench and testcase for each IP, and debugging on IP internal behavior. Reusing IP verification environment in SOC verification is always a desired methodology in theory but challenging in the implementation in reality. This paper presents a practical and efficient SOC verification flow by reusing IP test bench and test case based on UVM. SOC and IP Engineers work in their own specialized area and collaborate on debugging based on SOC-IP interface. It has been successfully used in project to decrease SOC verification complexity and debugging difficulty. Efficient flow shortens the verification cycle by 2 times and reduced engineer resources by 2 times.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. FLOW TO REUSE IP TESTBENCH AND TESTCASE IN SOC VERIFICATION
Ⅲ. PROJECTS IMPLEMENTATION
Ⅳ. RESULTS AND CONLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2014-569-000729894