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자료유형
학술저널
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대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.13 No.4
발행연도
2013.8
수록면
318 - 330 (13page)

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This paper presents a high-linearity low-noise small-size programmable gain amplifier (PGA) based on a new low-noise low-distortion differential amplifier and a proposed reconfiguration technique. The proposed differential amplifier combines an inverter-based differential pair with an adaptive biasing circuit to reduce noise and distortion. The reconfiguration technique saves the chip size by half by utilizing the same differential pair for the input transconductance and load-stage, interchangeably. Fabricated in 0.18- ㎛ CMOS, the proposed PGA shows a dB-linear control range of 21dB in 16 steps from-11dB to 10 dB with a gain error of less than ±0.33 dB, an IIP3 of 7.4~14.5 dBm, a P1dB of -7~1.2 dBm, a noise figure of 13dB, and a 3-dB bandwidth of 270㎒ at the maximum gain, respectively. The PGA occupies a chip area of 0.04㎟ and consumes only 1.3㎃ from the 1.8V supply.

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. LINEARITY ANALYSIS FOR INVERTER-BASED DIFFERENTIAL PAIR WITH ADAPTIVE BIASING
Ⅲ. NOISE ANALYSIS
Ⅳ. PROPOSED PGA WITH A NEW RECONFIGURATION TECHNIQUE
Ⅴ. MEASUREMENT RESULTS AND COMPARISIONS
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