Maintaining data coherency is critical issue in the embedded system. For example, when cache is used with other IP that has DMA feature, data inconsistency problem can be happened. This problem can be solved by setting non-cacheable region used by DMAC. However, there would be a drawback of performance degradation. So, in this paper, we propose reliable data transfer by doing cache flush operation before transaction of DMAC without data inconsistency. In the experiment, overall performance is improved about 1.37 times compared to the case without cache flush.