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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.3
- 발행연도
- 2014.6
- 수록면
- 345 - 355 (11page)
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초록· 키워드
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Today’s System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-tomarket requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. TEST INTERFACES FOR AMBA-BASED SOC
Ⅲ. IEEE 1500 WRAPPED CORES
Ⅳ. AMBA BASED PARALLEL SCAN TEST TECHNIQUE
Ⅴ. EXPERIMENTAL RESULTS
Ⅵ. CONCLUSIONS
REFERENCES
참고문헌 (19)
참고문헌 신청
1. [학술지(정기간행물)] - S. Narayanan / 1993 / Optimal configuring of multiple scan chains / Computers, IEEE Transactions on 42 : 1121 ~ 1131
2. [학술대회논문] - Z. Shanrui / 2004 / Cost-driven optimization of fault coverage in combined Built-In Self-Test/Automated Test Equipment testing / Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE 3 : 2021 ~ 2026
3. [학술대회논문] - S. K. Goel / 2002 / Effective and efficient test architecture design for SOCs / Test Conference, 2002. Proceedings. International : 529 ~ 538
4. [학술대회논문] - Y. Zorian / 1998 / Testing embedded-core based system chips / Test Conference, 1998. Proceedings., International : 130 ~ 143
5. [인터넷자원] - / / IEEE std 1500 Standard for Embedded Core Test
2. [학술대회논문] - Z. Shanrui / 2004 / Cost-driven optimization of fault coverage in combined Built-In Self-Test/Automated Test Equipment testing / Instrumentation and Measurement Technology Conference, 2004. IMTC 04. Proceedings of the 21st IEEE 3 : 2021 ~ 2026
3. [학술대회논문] - S. K. Goel / 2002 / Effective and efficient test architecture design for SOCs / Test Conference, 2002. Proceedings. International : 529 ~ 538
4. [학술대회논문] - Y. Zorian / 1998 / Testing embedded-core based system chips / Test Conference, 1998. Proceedings., International : 130 ~ 143
5. [인터넷자원] - / / IEEE std 1500 Standard for Embedded Core Test
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UCI(KEPA) : I410-ECN-0101-2015-560-002911159