지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 162 - 165 (4page)
이용수
초록· 키워드
오류제보하기
A full-speed USB 2.0 device PHY IP chip is implemented in FPGA by using a Verilog synthesis. It works successfully to interface a NAND flash chip to PC. It consists of a clock generator, TX and RX. The TX and RX circuits include a NRZI encoder/decoder, a bit stuffer/unstuffer and a serializer/deserializer. The clock generator accepts a 60㎒ clock and generates five 12㎒ clock signals which are spaced uniformly in time and synchronized to the 60㎒ clock. The five 12㎒ clocks are enable signals of TX and RX circuits. The 60㎒ clock is used as the clock signal of the TX and RX circuits. The 60㎒ clock are used for blind oversampling of CDR. An external 1.5kohm resistor is connected between the D+ node and VDD to notify the connection of the device PHY to the host PC.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE
Ⅲ. MEASUREMENTS
Ⅳ. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2016-569-001048721