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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2013.11
- 수록면
- 194 - 197 (4page)
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초록· 키워드
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In this paper, we propose a high-level synthesis algorithm with post-silicon delay tuning for RDR architectures. We first obtain a non-delayed scheduling/binding result and a delayed scheduling/binding result. By adding several extra functional units to vacant RDR islands, we have a delayed scheduling/binding result so that its latency cannot be increased compared with the non-delayed one. After that, we similarize the two scheduling/binding results by repeatedly modifying their results. We can finally realize non-delayed and delayed scheduling/binding results simultaneously on RDR architecture with almost no area/performance overheads and we can select either one of them depending on post-silicon delay variation. Experimental results show that our algorithm successfully reduces delayed scheduling/binding latency by up to 42.9% compared with the conventional approach.
목차
Abstract
1 Introduction
2 Problem Definition
3 A High-Level Synthesis Algorithm with Post-Silicon Delay Tuningfor RDR Architectures
4 Experimental Results
5 Conclusion
References
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UCI(KEPA) : I410-ECN-0101-2016-569-001048812