지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.6
- 발행연도
- 2014.12
- 수록면
- 760 - 767 (8page)
이용수
초록· 키워드
오류제보하기
This paper describes a high-radix crossbar switch design with low latency and power dissipation for Network-on-Chip (NoC) applications. The reduction in latency and power is achieved by employing a folded-clos topology, implementing the switch organized as three stages of low-radix switches connected in cascade. In addition, to facilitate the uniform placement of wires among the sub-switch stages, this paper proposes a Mux-Matrix-Mux structure, which implements the first and third switch stages as multiplexer-based crossbars and the second stage as a matrix-type crossbar. The proposed 256-radix, 8-bit crossbar switch designed in a 65㎚ CMOS has the simulated power dissipation of 1.92-W and worst-case propagation delay of 0.991-ns while operating at 1.2-V supply and 500-㎒ frequency. Compared with the state-of-the-art designs in literature, the proposed crossbar switch achieves the best energy-delay-area efficiency of 0.73-fJ/cycle·㎱·λ².
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED FOLDED-CLOS CROSSBAR SWITCH ARCHITECTURE
Ⅲ. CIRCUIT IMPLEMENTATION
Ⅳ. SIMULATION RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (9)
참고문헌 신청
1. [학술대회논문] - T. Wu / 2002 / A 2Gb/s 256*256 CMOS Crossbar Switch Fabric Core Design using Pipelined MUX / proc. International Symposium on Circuits and Systems (ISCAS) : 568 ~ 572
2. [학술대회논문] - K. Choi / 1992 / VLSI Implementation of a 256x256 Crossbar Interconnection Network / proc. International Parallel Processing Symposium (IPPS) : 289 ~ 293
3. [학위논문] - I. Shamim / 2009 / Energy Efficient Links and Routers for Multi-Processor Computer Systems / 석사 / Massachusetts Institute of Technology
4. [학술대회논문] - D. Song / 2013 / A Low-Power High-Radix Switch Fabric Based on Low-Swing Signaling and Partially-Activated Input Lines / proc. VLSI Design, Automation, and Test (VLSI-DAT) : 1 ~ 4
5. [학술대회논문] - J. Ryoo / 2012 / Design of Low-Power High-Radix Switch Fabric with Partially-Activated Input and Output Lines / International SoC Design Conf. (ISOCC) : 227 ~ 230
2. [학술대회논문] - K. Choi / 1992 / VLSI Implementation of a 256x256 Crossbar Interconnection Network / proc. International Parallel Processing Symposium (IPPS) : 289 ~ 293
3. [학위논문] - I. Shamim / 2009 / Energy Efficient Links and Routers for Multi-Processor Computer Systems / 석사 / Massachusetts Institute of Technology
4. [학술대회논문] - D. Song / 2013 / A Low-Power High-Radix Switch Fabric Based on Low-Swing Signaling and Partially-Activated Input Lines / proc. VLSI Design, Automation, and Test (VLSI-DAT) : 1 ~ 4
5. [학술대회논문] - J. Ryoo / 2012 / Design of Low-Power High-Radix Switch Fabric with Partially-Activated Input and Output Lines / International SoC Design Conf. (ISOCC) : 227 ~ 230
이 논문의 저자 정보
최근 본 자료
댓글(0)
0
UCI(KEPA) : I410-ECN-0101-2016-569-001112522