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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.15 No.2
- 발행연도
- 2015.4
- 수록면
- 155 - 167 (13page)
이용수
초록· 키워드
오류제보하기
An adaptive equalization scheme based on all-digital jitter measurement is proposed for a continuous time linear equalizer (CTLE) preceding a clock and data recovery (CDR) in a receiver circuit for high-speed serial interface. The optimum equalization coefficient of CTLE is determined during the initial training period based on the measured jitter. The proposed circuit finds automatically the optimum equalization coefficient for CTLE with 20”, 30”, 40” FR4 channel at the data rate of 5 Gbps. The chip area of the equalizer including the adaptive controller is 0.14 mm2 in a 0.13 μm process. The equalizer consumes 12 mW at 1.2 V supply during the normal operation. The adaptive equalizer has been applied to a USB3.0 receiver.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. PROPOSED ADAPTIVE ALGORITHM
Ⅲ. CIRCUIT IMPLEMENTATION
Ⅳ. MEASUREMENT RESULTS
Ⅴ. CONCLUSIONS
REFERENCES
참고문헌 (20)
참고문헌 신청
1. [학술지(정기간행물)] - T. Beukema / 2005 / A 6.4 Gb/s CMOS SerDes core with feed-forward and decision-feedback equalization / IEEE J. Solid-State Circuits : 2633 ~ 2645
2. [학술대회논문] - M. Meghelli / 2006 / A 10 Gb/s 5- Tap-DFE/4-Tap-FFE transceiver in 90 nm CMOS / IEEE Int.Solid-State Circuits Conf. Dig. Tech. Papers : 80 ~ 81
3. [학술지(정기간행물)] - R. Payne / 2005 / A 6.25-Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels / IEEE J. Solid-State Circuits 40 : 2646 ~ 2657
4. [학술지(정기간행물)] - V. Balan / 2005 / A 4.8–6.4-Gb/s serial link for backplane applications using decision feedback equalization / IEEE J.Solid-State Circuits 40 (9) : 1957 ~ 1967
5. [학술지(정기간행물)] - H.-J. Chi / 2011 / A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface / IEEE J.Solid-State Circuits 46 (9) : 897 ~ 910
2. [학술대회논문] - M. Meghelli / 2006 / A 10 Gb/s 5- Tap-DFE/4-Tap-FFE transceiver in 90 nm CMOS / IEEE Int.Solid-State Circuits Conf. Dig. Tech. Papers : 80 ~ 81
3. [학술지(정기간행물)] - R. Payne / 2005 / A 6.25-Gb/s Binary Transceiver in 0.13-μm CMOS for Serial Data Transmission Across High Loss Legacy Backplane Channels / IEEE J. Solid-State Circuits 40 : 2646 ~ 2657
4. [학술지(정기간행물)] - V. Balan / 2005 / A 4.8–6.4-Gb/s serial link for backplane applications using decision feedback equalization / IEEE J.Solid-State Circuits 40 (9) : 1957 ~ 1967
5. [학술지(정기간행물)] - H.-J. Chi / 2011 / A Single-Loop SS-LMS Algorithm With Single-Ended Integrating DFE Receiver for Multi-Drop DRAM Interface / IEEE J.Solid-State Circuits 46 (9) : 897 ~ 910
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UCI(KEPA) : I410-ECN-0101-2016-569-001461724