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논문 기본 정보

자료유형
학술저널
저자정보
Fengwei An (Hiroshima University) Keisuke Mihara (Hiroshima University) Shogo Yamasaki (Hiroshima University) Lei Chen (Hiroshima University) Hans Jürgen Mattausch (Hiroshima University)
저널정보
대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.4
발행연도
2016.8
수록면
405 - 414 (10page)

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초록· 키워드

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IC-implementations provide high performance for solving the high computational cost of pattern matching but have relative low flexibility for satisfying different applications. In this paper, we report an associative memory architecture for k nearest neighbor (KNN) search, which is one of the most basic algorithms in pattern matching. The designed architecture features reconfigurable vector-component parallelism enabled by programmable switching circuits between vector components, and a dedicated majority vote circuit. In addition, the main time-consuming part of KNN is solved by a clock mapping concept based weighted frequency dividers that drastically reduce the in principle exponential increase of the worst-case search-clock number with the bit width of vector components to only a linear increase. A test chip in 180 ㎚ CMOS technology, which has 32 rows, 8 parallel 8-bit vector-components in each row, consumes altogether in peak 61.4 ㎽ and only 11.9 mW for nearest squared Euclidean distance search (at 45.58 ㎒ and 1.8 V).

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. RECONFIGURABLE WORD-PARALLEL ARCHITECTURE FOR KNN
Ⅲ. CHIP REALIZATION AND EXPERIMENTAL RESULTS
Ⅴ. CONCLUSIONS
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