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논문 기본 정보

자료유형
학술저널
저자정보
Hongjin Kim (Sungkyunkwan University) Young-Jun Park (Sungkyunkwan University) Ju-Hyun Park (Sungkyunkwan University) Ho-Cheol Ryu (Sungkyunkwan University) Young-Gun Pu (Sungkyunkwan University) Minjae Lee (Gwangju Institute of Science and Technology) Keumcheol Hwang (Sungkyunkwan University) Younggoo Yang (Sungkyunkwan University) Kang-Yoon Lee (Sungkyunkwan University)
저널정보
전력전자학회 JOURNAL OF POWER ELECTRONICS JOURNAL OF POWER ELECTRONICS Vol.16 No.6
발행연도
2016.11
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2,024 - 2,034 (11page)

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This paper presents a DC-DC buck converter with a Phase-Locked Loop (PLL) that can compensates for power efficiency degradation over a wide input range. Its switching frequency is kept at 2 ㎒ and the delay difference between the High side driver and the Low side driver can be minimized with respect to Process, Voltage and Temperature (PVT) variations by adopting the PLL. The operation mode of the proposed DC-DC buck converter is automatically changed to Pulse Width Modulation (PWM) or PWM frequency modes according to the load condition (heavy load or light load) while supporting a maximum load current of up to 1.2 A. The PWM frequency mode is used to extend the CCM region under the light load condition for the PWM operation. As a result, high efficiency can be achieved under the light load condition by the PWM frequency mode and the delay compensation with the PLL. The proposed DC-DC buck converter is fabricated with a 0.18 ㎛ BCD process, and the die area is 3.96 ㎟. It is implemented to have over a 90 % efficiency at an output voltage of 5 V when the input range is between 8 V and 20 V. As a result, the variation in the power efficiency is less than 1 % and the maximum efficiency of the proposed DC-DC buck converter with the PLL is 95.4 %.

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. ARCHITECTURE OF THE DC-DC BUCK CONVERTER WITH A PLL
Ⅲ. EXPERIMENTAL RESULTS
Ⅳ. CONCLUSION
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