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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 한국정보통신학회 INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING 2014 INTERNATIONAL CONFERENCE ON FUTURE INFORMATION & COMMUNICATION ENGINEERING Vo.6 No.1
- 발행연도
- 2014.6
- 수록면
- 311 - 314 (4page)
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초록· 키워드
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In this paper, it will empower the chip designers, for the first time, to optimize power simultaneously with area and speed at the early stages. This paper is the first attempt to the behavioral level synthesis of non-zero clock skew designs. First, we show that the register binding in behavioral level synthesis stage has a significant impact on the clocking constraints between registers. As a result, different register binding solutions lead to different smallest feasible clock periods. Based on this observation, we present a synthesis methodology that is power-management-aware, i.e., it generates a schedule that maximizes the potential for power management in the resulting hardware. The effectiveness of the proposed algorithm has been proven by the experiment with the benchmark examples
목차
Abstract
I. INTRODUCTION
II. A NEW EFFICIENT SYNTHESIS OPTIMIZATION METHODOLOGY
III. EXPERIMENTAL RESULTS
IV. CONCLUSIONS
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2018-004-000962637