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논문 기본 정보

자료유형
학술저널
저자정보
Chainarin Ekkaravarodome (King Mongkut’s University of Technology North Bangkok) Phatiphat Thounthong (King Mongkut’s University of Technology North Bangkok) Kamon Jirasereeamornkul (King Mongkut’s University of Technology Thonburi)
저널정보
대한전기학회 Journal of Electrical Engineering & Technology Journal of Electrical Engineering & Technology Vol.13 No.3
발행연도
2018.5
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1,251 - 1,264 (14page)

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초록· 키워드

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The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for 220-V<SUB>rms</SUB>/50-Hz utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

목차

Abstract
1. Introduction
2. Proposed Topology
3. Design of Proposed Topology
4. Simulation and Experimental Results
5. Conclusion
References

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