지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.3
- 발행연도
- 2019.6
- 수록면
- 260 - 269 (10page)
- DOI
- 10.5573/JSTS.2019.19.3.260
이용수
초록· 키워드
오류제보하기
Invasive physical attacks on integrated circuits (ICs), such as de-packaging, focused ion beam (FIB) chip editing, and micro-probing attempts, constitute security threats for chips with potentially valuable information, such as smart cards. Using a state-of-the-art circuit-editing technique, an attacker can remove an IC’s top metal layer, leaving its secure information exposed to micro-probing attacks. Security ICs can be seriously threatened by such attacks and thus require on-chip countermeasures. Conventional active shields, however, have difficulty coping with physical attacks based on FIB chip editing (i.e., bypassing the top metal shield). This study presents a novel countermeasure against physical attacks based on the use of a reconfigurable metal shield for both top metal removal and microprobing attack detection. This shield consists of two circuits: an FIB chip editing detection circuit consisting of a random number generator and a micro-probing attempt detection circuit consisting of two conditionally synchronized ring oscillators. Both circuits share a randomly reconfigured top metal shield, which represents a promising solution for security against state-of-the-art invasive attacks.
목차
Abstract
I. INTRODUCTION
II. RECONFIGURABLE TOP METAL SHIELD
III. EXPERIMENTAL RESULTS
IV. CONCLUSIONS
REFERENCES
참고문헌 (20)
참고문헌 신청
S. Lucero, “IoT Platforms - Enabling the Internet of Things, Complimentary Whitepaper,” IHS Technology, Mar., 2016.
S. Blythe, B. Fraboni, S. Lall, H. Ahmed, and U. de Riu, “Layout reconstruction of complex silicon chips,” Solid-State Circuits, IEEE Journal of, vol. 28, no. 2, pp. 138?145, Feb., 1993.
O. Kommerling and M. G. Kuhn, “Design principles for tam-perresistant smartcard processors,” USENIX Workshop of Smartcard Technology (WOST), pp. 9?20, 1999.
S. Skorobogatov, “Physical attacks on tamper resistance: progress and lessons,” 2nd ARO Special Workshop on Hardware Assurance, 2011.
S. Briais, J.-M. Cioranesco, J.-L. Danger, S. Guilley, D. Naccache, and T. Porteboeuf, “Random active shield,” Workshop FDTC, pp. 103?114, 2012.
S. Blythe, B. Fraboni, S. Lall, H. Ahmed, and U. de Riu, “Layout reconstruction of complex silicon chips,” Solid-State Circuits, IEEE Journal of, vol. 28, no. 2, pp. 138?145, Feb., 1993.
O. Kommerling and M. G. Kuhn, “Design principles for tam-perresistant smartcard processors,” USENIX Workshop of Smartcard Technology (WOST), pp. 9?20, 1999.
S. Skorobogatov, “Physical attacks on tamper resistance: progress and lessons,” 2nd ARO Special Workshop on Hardware Assurance, 2011.
S. Briais, J.-M. Cioranesco, J.-L. Danger, S. Guilley, D. Naccache, and T. Porteboeuf, “Random active shield,” Workshop FDTC, pp. 103?114, 2012.
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