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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국전기전자재료학회 Transactions on Electrical and Electronic Materials Transactions on Electrical and Electronic Materials 제15권 제6호
- 발행연도
- 2014.1
- 수록면
- 309 - 314 (6page)
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This work proposes an integrated high frequency divider with an inductive peaking technique implemented ina current mode logic (CML) frequency divider. The proposed divider is composed with a master-slave flip-flop,and the master-slave flip-flop acts as a latch and read circuits which have the differential pair and cross-coupledn-MOSFETs. The cascode bias is applied in an inductive peaking circuit as a current source and the cascode bias isused for its high current driving capability and stable frequency response. The proposed divider is designed with0.18-μm CMOS process, and the simulation used to evaluate the divider is performed with phase-locked loop (PLL)circuit as a feedback circuit. A divide-by-two operation is properly performed at a high frequency of 20 GHz. In theoutput frequency spectrum of the PLL, a peak frequency of 2 GHz is obtained witha divide-by-eight circuit at an inputfrequency of 250 MHz. The reference spur is obtained at -64 dBc and the power consumption is 13 mW.
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참고문헌 (10)
참고문헌 신청
C. Cao / 2005 / / IEEE Mic. and Wireless Comp. Letters 15 : 721 ~
C. Lee / 2013 / / IEEE Trans. Power Electronics 28 : 2596 ~
H. D. Wohlmuth / 2002 / / Proc. ESSCIRC 2002 : 823 ~
J. C. Chien / 2006 / / Micro. and Wireless Com. Letters 16 : 558 ~
J. H. Kim / 2009 / / IEEE Trans. Circuit and Systems-1 56 : 2544 ~
C. Lee / 2013 / / IEEE Trans. Power Electronics 28 : 2596 ~
H. D. Wohlmuth / 2002 / / Proc. ESSCIRC 2002 : 823 ~
J. C. Chien / 2006 / / Micro. and Wireless Com. Letters 16 : 558 ~
J. H. Kim / 2009 / / IEEE Trans. Circuit and Systems-1 56 : 2544 ~
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