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논문 기본 정보

자료유형
학술대회자료
저자정보
Nwe Zin Oo (Prince of Songkla University) Panyayot Chaikan (Prince of Songkla University)
저널정보
제어로봇시스템학회 제어로봇시스템학회 국제학술대회 논문집 ICCAS 2021
발행연도
2021.10
수록면
307 - 310 (4page)

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Today’s modern computers support multi-core processors architecture that enhances parallel computing with single instruction multiple data computing. According to memory structure, the CPU core performance is a vital role in power-saving profiling across the multi-core architecture. Although CPU parking was controlled entirely by the operating system of both laptops and desktops computers, the performance can be boost by tweaking CPU core parking and changing frequency scaling in real-time. In this paper, the effect of core parking for parallel matrix-matrix multiplication on shared memory is proposed by utilizing AVX and OpenMP. When the large matrix sizes are multiplied parallelly on shared memory, the overheads of memory capacity and data transferring become the main issues not only for increased power consumption but also for decrease performance. The large square matrix multiplications are tested that range from 1024×1024 to 16384×16384 by utilizing Advanced Vector Extensions (AVX) intrinsics and OpenMP, and varying the different power-saving profiling dynamically. The default power-saving profile in a computer is the balanced mode and we tested for performance by tweaking CPU parking with four different modes (Balanced, High Performance, Bitsum Highest Performance, and Power Saving). According to tested results, the Bitsum Highest Performance mode obtained the maximum performance and minimum power and energy consumption than other profiling modes.

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Abstract
1. INTRODUCTION
2. Theory Background and Advanced Vector Extensions (AVX)
3. CPU Core Parking
4. EXPERIMENTAL RESULTS
5. CONCLUSION
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