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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 한국정보통신학회JICCE Journal of information and communication convergence engineering Journal of information and communication convergence engineering Vol.13 No.3
- 발행연도
- 2015.9
- 수록면
- 180 - 188 (9page)
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초록· 키워드
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As a potential alternative to the complementary metal-oxide semiconductor (CMOS) technology, many researchers are focusing on carbon-nanotube field-effect transistors (CNFETs) for future electronics. However, existing studies report the advantages of CNFETs over CMOS at the device level by using small-scale circuits, or over outdated CMOS technology. In this paper, we propose a methodology of analyzing CNFET-based circuits and study its impact at the full-chip scale. First, we design CNFET standard cells and use them to construct large-scale designs. Second, we perform parasitic extraction of CNFET devices and characterize their timing and power behaviors. Then, we perform a full-chip analysis and show the benefits of CNFET over CMOS in 45-nm and 20-nm designs. Our full-chip study shows that in the 45-nm design, CNFET circuits achieve a 5.91×/3.87× (delay/power) benefit over CMOS circuits at a density of 200 CNTs/μm. In the 20-nm design, CNFET achieves a 6.44×/3.01× (delay/power) benefit over CMOS at a density of 200 CNTs/μm.
목차
Abstract
I. INTRODUCTION
II. PRELIMINARIES
III. CNFET PARASITIC EXTRACTION
IV. 45-NM FULL-CHIP RESULTS
V. 20-NM FULL-CHIP RESULTS
VI. CONCLUSION
REFERENCES
참고문헌 (18)
참고문헌 신청
[학술지(정기간행물)] - S. I. Sayed / 2013 / Performance optimization of logic circuits based on hybrid CMOS and CNFET design / International Journal of Recent Technology and Engineering 1 (6) : 1 ~ 4
[학술지(정기간행물)] - J. Deng / 2007 / A compact SPICE model for carbonnanotube field-effect transistors including nonidealities and its application. Part II : Full device model and circuit performance benchmarking / IEEE Transactions on Electron Devices 54 (12) : 3195 ~ 3205
[학술지(정기간행물)] - A. D. Franklin / 2012 / Sub-10 nm carbon nanotube transistor / Nano Letters 12 (2) : 758 ~ 762
[학술지(정기간행물)] - N. Patil / 2011 / Scalable carbon nanotube computational and storage circuits immune to metallic and mispositioned carbon nanotubes / IEEE Transactions on Nanotechnology 10 (4) : 744 ~ 750
[학술대회논문] - J. Zhang / 2010 / Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement / Proceedings of the 47th Design Automation Conference (DAC2010) : 889 ~ 892
[학술지(정기간행물)] - J. Deng / 2007 / A compact SPICE model for carbonnanotube field-effect transistors including nonidealities and its application. Part II : Full device model and circuit performance benchmarking / IEEE Transactions on Electron Devices 54 (12) : 3195 ~ 3205
[학술지(정기간행물)] - A. D. Franklin / 2012 / Sub-10 nm carbon nanotube transistor / Nano Letters 12 (2) : 758 ~ 762
[학술지(정기간행물)] - N. Patil / 2011 / Scalable carbon nanotube computational and storage circuits immune to metallic and mispositioned carbon nanotubes / IEEE Transactions on Nanotechnology 10 (4) : 744 ~ 750
[학술대회논문] - J. Zhang / 2010 / Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement / Proceedings of the 47th Design Automation Conference (DAC2010) : 889 ~ 892
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