지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 류지열
- 발행연도
- 2014
- 저작권
- 부경대학교 논문은 저작권에 의해 보호받습니다.
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초록· 키워드
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The recent advance in ubiquitous technology has grown many changes in human life. Variety of informations that exist in nature are provided to people with the USN(Ubiquitous Sensor Network). The information includes analog signal of various types, and there are many difficulties to process the various analog informations. To solve these problems, ADC(Analog-to-Digital Converter) is required in USN.
This thesis presents the design of SAR(Successive Approximation Register) ADC for USN. The proposed SAR ADC consists of sample-and-hold stage, capacitor array network stage, SAR control logic stage, comparator stage, DAC stage and DAC control logic stage. This SAR ADC is designed to have performance of 12-bit resolution and 1MSps(1 Mega Sampling per second). The proposed circuit is designed using Magnachip/SK Hynix 0.18μm CMOS 1Poly-6Metal process, and it is powered by 1.8V supply. To reduce chip area and power dissipation, we minimized unit capacitor area and number of the total capacitors, and designed the circuit considering optimization as compared to conventional circuits. The proposed circuit in this thesis showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.03dB, and excellent effective bit number of 11.34-bit as compared to conventional research results. The designed circuit also showed low power dissipation of 3.24mW, and small chip area of 0.56mm². The proposed ADC is applicable for the signal conversion of the industry system application.
This thesis presents the design of SAR(Successive Approximation Register) ADC for USN. The proposed SAR ADC consists of sample-and-hold stage, capacitor array network stage, SAR control logic stage, comparator stage, DAC stage and DAC control logic stage. This SAR ADC is designed to have performance of 12-bit resolution and 1MSps(1 Mega Sampling per second). The proposed circuit is designed using Magnachip/SK Hynix 0.18μm CMOS 1Poly-6Metal process, and it is powered by 1.8V supply. To reduce chip area and power dissipation, we minimized unit capacitor area and number of the total capacitors, and designed the circuit considering optimization as compared to conventional circuits. The proposed circuit in this thesis showed high SNDR(Signal-to-Noise Distortion Ratio) of 70.03dB, and excellent effective bit number of 11.34-bit as compared to conventional research results. The designed circuit also showed low power dissipation of 3.24mW, and small chip area of 0.56mm². The proposed ADC is applicable for the signal conversion of the industry system application.
목차
Abstract···················································iv제1장 서 론···················································1제2장 ADC 기본 개념 및 동작원리···················································32.1 ADC의 구조 및 동작원리···················································32.2 ADC의 주요 성능지수 및 수식··················································62.3 SAR ADC 구조 및 동작원리···················································7제3장 제안된 SAR ADC 회로 및 해석···········································133.1 샘플-앤-홀드 단···················································143.2 커패시터 어레이 네트워크 단·················································163.3 비교기 단···················································203.4 SAR 제어 로직 단···················································213.5 DAC 제어 로직 단···················································223.6 DAC 단···················································233.7 SAR ADC···················································24제4장 결과 및 분석···················································264.1 SAR ADC 시뮬레이션 분석···················································264.2 SAR ADC 구현 및 성능 평가···················································34제5장 결 론···················································36참고문헌···················································37별첨···················································39
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