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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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- 2015
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Model Parameter Extraction and Overlap Capacitance SPICE Modeling for RF MOSFETs
The gate electrode resistance is directly extracted by using a Z-parameter equation at the zero bias without bias-dependent data fitting. In addition, the non-quasi-static capacitance previously extracted by fitting S-parameters is simply and accurately extracted by using a Y-parameter equation. The extracted parameter values are proven to be physically reasonable by comparing modeled input impedance with measured one up to 40GHz. RF MOSFET small-signal equivalent circuit modeling with metal interconnect inductances is performed. The inductance effect on frequency-dependent characteristics of Y-parameters is analyzed in detail. From this analysis, it is observed that the effective capacitance increases with increasing frequency. This frequency effect is proven to be caused by the interconnect inductance. The inaccuracy of the bias-dependent gate-drain overlap capacitance Cgdo simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. In order to improve the conventional models, a new BSIM4 macro model with a physical bias-dependent Cgdo equation is proposed and its accuracy is validated in the full bias range.
The gate electrode resistance is directly extracted by using a Z-parameter equation at the zero bias without bias-dependent data fitting. In addition, the non-quasi-static capacitance previously extracted by fitting S-parameters is simply and accurately extracted by using a Y-parameter equation. The extracted parameter values are proven to be physically reasonable by comparing modeled input impedance with measured one up to 40GHz. RF MOSFET small-signal equivalent circuit modeling with metal interconnect inductances is performed. The inductance effect on frequency-dependent characteristics of Y-parameters is analyzed in detail. From this analysis, it is observed that the effective capacitance increases with increasing frequency. This frequency effect is proven to be caused by the interconnect inductance. The inaccuracy of the bias-dependent gate-drain overlap capacitance Cgdo simulation in original BSIM4 and BSIM4 macro model using a diode is analyzed in detail. In order to improve the conventional models, a new BSIM4 macro model with a physical bias-dependent Cgdo equation is proposed and its accuracy is validated in the full bias range.
목차
Ⅰ. 서론 11.1. 최근 동향 및 연구의 중요성 11.2. 기존 NQS 및 BSIM4 SPICE overlap 캐패시턴스 모델의 문제점 21.3. 본 연구의 범위 3Ⅱ. 패드 및 금속배선 de-embedding 5Ⅲ. RF MOSFET NQS gate-source 임피던스의 개선된 모델링 93.1. Non-Quasi-Static gate electrode 저항 직접 추출방법 93.2. Non-Quasi-Static gate-source 캐패시턴스 직접 추출방법 15Ⅳ. 금속배선 인덕턴스가 주파수 종속 Y-파라미터에 미치는 영향분석 234.1. 모델 파라미터 추출 234.2. 인덕턴스 효과 분석 27Ⅴ. 전압종속 gate-drain overlap 캐패시턴스 SPICE 모델링 315.1. 전압종속 gate-drain overlap 캐패시턴스 SPICE 모델 분석 315.2. 전압종속 gate-drain overlap 캐패시턴스의 새로운 SPICE 모델링 375.3. 새로운 모델의 정확도 분석 43Ⅵ. 결론 45Ⅶ. 참고 문헌 47
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