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ABSTRACT
A Study on Parallel Processing of Lane Detection Algorithms Based on Multi-core Processor
Hyo-Chan Lee
Department of Information and Communication Engineering,
The Graduate School Hoseo University
Asan, Korea
(Supervised by Professor Dai-Tchul MOON)
In this paper, Lane detection Parallel processing based on Multi-core platform is proposed. From the results of data level parallelized algorithm based on octa-core, it has shown 3.3 times performance improvement compared to the performance using single-core platform. However, due to the bottleneck, use of 8 core did not respond with 8 times performance improvement. Therefore, in this paper, I suggest high-speed data level parallelized algorithm. The parallelism was processed after removing the bottleneck and disassembling it into unit base in the data level parallelism. The research was conducted on a multi-cored general purpose PC. In addition, Window Resource Monitor and Timer was used for performance measuring. As a result, high-speed data level parallelized algorithm has shown 5 times speed improvement compared to the performance using single-core platform.
A Study on Parallel Processing of Lane Detection Algorithms Based on Multi-core Processor
Hyo-Chan Lee
Department of Information and Communication Engineering,
The Graduate School Hoseo University
Asan, Korea
(Supervised by Professor Dai-Tchul MOON)
In this paper, Lane detection Parallel processing based on Multi-core platform is proposed. From the results of data level parallelized algorithm based on octa-core, it has shown 3.3 times performance improvement compared to the performance using single-core platform. However, due to the bottleneck, use of 8 core did not respond with 8 times performance improvement. Therefore, in this paper, I suggest high-speed data level parallelized algorithm. The parallelism was processed after removing the bottleneck and disassembling it into unit base in the data level parallelism. The research was conducted on a multi-cored general purpose PC. In addition, Window Resource Monitor and Timer was used for performance measuring. As a result, high-speed data level parallelized algorithm has shown 5 times speed improvement compared to the performance using single-core platform.
목차
목 차Ⅰ. 서 론 1Ⅱ. 차선검출 시스템 개발 51. 차선검출 알고리즘 5가. Gaussian Smoothing Filter 7나. Gray Scale Conversion 10다. Sobel Edge Detection 12라. Hough Transform 152. 차선검출 시스템 개발 환경 19가. 시스템 개발 환경 19나. 임베디드 플랫폼 개발 21a. Aldebaran CPU기반의 임베디드 플랫폼 21b. 웹 기반 온라인 설계 개발환경 22Ⅲ. 멀티코어 기반의 병렬화 차선검출 알고리즘 261. OpenMP 라이브러리 272. 데이터 레벨 기반의 차선검출 설계 313. 제안하는 고속 데이터 레벨 알고리즘 34
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