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논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 장영찬
- 발행연도
- 2018
- 저작권
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이 논문의 연구 히스토리 (3)
2018
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This thesis presents a sigma-delta analog modulator for sensor interface. The proposed sigma-delta analog modulator, which has an architecture of cascade of integrator feedback (CIFB), consists of three switched-capacitor integrators, a single-bit comparator, and a non-overlapped clock generator. The behavioral simulations using Matlab are achieved to evaluate the performance of an architecture that is used for the sigma-delta analog modulator. Furthermore, the design specification of each block is determined performing the HSpice simulation using ideal model. A switched-capacitor common-mode feedback circuit is adopted to reduce the power consumption of fully differential operational transconductance amplifier (OTA). The capacitor values of integrators are determined using a kT/C noise model, and a non-overlapped clock for integrators improves the signal to noise and distortion ratio by suppressing the charge injection noise.
The proposed third-order sigma-delta analog modulator which is designed using 0.11-㎛ CMOS process with 1.2 V supply voltage. When the sampling frequency and oversampling ratio are 4 MHz and 128, the simulated SNDR is 99.07 dB for the signal band of 15.625 kHz. The active area and power consumption of the designed sigma-delta analog modulator are 0.145 ㎟ and 341 ㎼, respectively.
The proposed third-order sigma-delta analog modulator which is designed using 0.11-㎛ CMOS process with 1.2 V supply voltage. When the sampling frequency and oversampling ratio are 4 MHz and 128, the simulated SNDR is 99.07 dB for the signal band of 15.625 kHz. The active area and power consumption of the designed sigma-delta analog modulator are 0.145 ㎟ and 341 ㎼, respectively.
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