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- 학위논문
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- 지도교수
- 노의철
- 발행연도
- 2019
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Modular multi-level converter (MMC) has many advantages such as low harmonic, large power capacity and high reliability. Therefore, it has been actively researched and widely used for the variety of applications including the high voltage direct current (HVDC) transmission.
The basic element of the MMC based HVDC system is submodule, therefore, it is necessary to test the submodule before the construction of the HVDC system. Therefore, IEC 62501 suggested the requirements of the electrical type testing for the voltage sourced converter (VSC) valves for MMC based HVDC transmission. In order to satisfy the requirement, research works have been done to provide the testing schemes for the submodule and the valve. The submodule input current contains not only AC (Alternating Current) but also DC (Direct Current) component in real operating HVDC transmission. However, the submodule input current of the conventional test circuit has only AC component, therefore, it is not exactly the same with the real system.
This paper proposes new submodule test circuits those submodule input current contains DC component as well as AC component. The first proposed scheme has the ability to test both rectifier side submodule and inverter side submodule at the same time. The design procedure for the capacitor consisting the test circuit is described. The second scheme can control the submodule capacitor voltage to be maintained constant. The operating principle of those schemes is described, and simulation and scale down experiment are carried out.
The simulation and experimental results show the usefulness of the proposed schemes.
The basic element of the MMC based HVDC system is submodule, therefore, it is necessary to test the submodule before the construction of the HVDC system. Therefore, IEC 62501 suggested the requirements of the electrical type testing for the voltage sourced converter (VSC) valves for MMC based HVDC transmission. In order to satisfy the requirement, research works have been done to provide the testing schemes for the submodule and the valve. The submodule input current contains not only AC (Alternating Current) but also DC (Direct Current) component in real operating HVDC transmission. However, the submodule input current of the conventional test circuit has only AC component, therefore, it is not exactly the same with the real system.
This paper proposes new submodule test circuits those submodule input current contains DC component as well as AC component. The first proposed scheme has the ability to test both rectifier side submodule and inverter side submodule at the same time. The design procedure for the capacitor consisting the test circuit is described. The second scheme can control the submodule capacitor voltage to be maintained constant. The operating principle of those schemes is described, and simulation and scale down experiment are carried out.
The simulation and experimental results show the usefulness of the proposed schemes.
목차
1.서론 12.서브모듈 성능 시험회로 분석 42.1.MMC 기반 HVDC 시스템의 암 전류 분석 42.2.암 전류와 서브모듈 커패시터 전압에 대한 분석 102.3.서브모듈 성능 시험회로의 필요조건 133.서브모듈 성능 시험회로 183.1.서브모듈 성능 시험회로-1 183.1.1.서브모듈 성능 시험회로-1의 구조 183.1.2.서브모듈 성능 시험회로-1의 동작 분석 203.1.3.서브모듈 성능 시험회로-1의 설계 및 시뮬레이션 결과 233.2.서브모듈 성능 시험회로-2 313.2.1.서브모듈 성능 시험회로-2의 구조 313.2.2.서브모듈 성능 시험회로-2의 동작 분석 333.2.3.서브모듈 성능 시험회로-2의 설계 및 제어기법 373.2.4.서브모듈 성능 시험회로-2의 시뮬레이션 결과 404.축소모형 실험 결과 444.1.서보모듈 성능 시험회로-1의 축소모형 실험 결과 444.2.서브모듈 성능 시험회로-2의 축소모형 실험 결과 495.결론 53참고 문헌 54감사의 글 58
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