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논문 기본 정보
- 자료유형
- 학위논문
- 저자정보
- 지도교수
- 문병인
- 발행연도
- 2021
- 저작권
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초록· 키워드
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In communication and memory systems, ECC based on BCH code is being used and studied to improve data reliability, security, and memory productivity. The addition of ECC operations during data processing leads to an increase in latency. In the future, communication and memory systems that will become faster as technology advances will require shorter latency for ECC. However, the Berlekamp-Massey Algorithm (BMA) that generates the error locator polynomial of the BCH code requires repetitive computation as much as the error correction capability. So, it has the most complex and long latency among BCH code operations. This paper presents a method of reducing the latency of BCH-based BMA and iBMA (inversionless BMA) pipelined circuits. The initial stage of BMA and iBMA can be calculated as a combination of the input syndrome. In this way, this paper proposes a method to reduce latency by omitting the first stage of BMA and iBMA.
The proposed method can reduce latency as much as the time required for one stage of BMA and iBMA. In addition, double error correction has a shorter latency than systolic iBMA, which is known to be the fastest. Through this study, it will be helpful for multiple error correction ECC to be applied to next-generation communication and memory systems.
The proposed method can reduce latency as much as the time required for one stage of BMA and iBMA. In addition, double error correction has a shorter latency than systolic iBMA, which is known to be the fastest. Through this study, it will be helpful for multiple error correction ECC to be applied to next-generation communication and memory systems.
목차
1. 서론 12. BCH 부호 32.1 부호화 62.2 복호화 72.2.1 Syndrome 생성 72.2.2 오류 위치 다항식 생성 82.2.3 오류 위치 탐색 및 정정 143. 제안하는 방법 153.1 Berlekamp-Massey algorithm 153.2 Inversionless Berlekamp-Massey algorithm 184. 실험 및 결과 215. 결론 26
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