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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 511 - 514 (4page)
이용수
초록· 키워드
오류제보하기
A CMOS vector summation circuit using the square-law characteristic of MOS transistors in saturation is presented. This circuit is widely used in communication, in order to analyze and processing the signal. The previous papers proposed to use the translinear of bipolar transistor, operational amplifier or current conveyor. The paper proposes to design the vector summation circuit by using MOS transistors and suitable for integrated circuit.
목차
Abstract
1. Introduction
2. Principle of operation
3. Simulation Results
5. Conclusion
References
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