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논문 기본 정보

자료유형
학술대회자료
저자정보
Jae Woong Chun (Syracuse University) C. Y. Roger Chen (Syracuse University)
저널정보
대한전자공학회 대한전자공학회 ISOCC ISOCC 2010 Conference
발행연도
2010.11
수록면
119 - 122 (4page)

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Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due to the high transistor density, reduced voltage and oxide thickness. We first experimentally investigate existing low-power techniques and point out problems with them. We then propose a family of circuit types for low-power design centered around inserting controlling transistors between pull-up and pull down circuits as well as between pull-up circuits/pull down circuits and power/ground. We investigate the characteristics of proposed gate types in terms of ability to
reduce power consumption and their associated delay overhead. In addition, several variations of drain gating are discussed. In the end, an overall procedure for low-power circuit design is proposed by intelligently mixing various proposed circuit types for gates in the circuits based upon gate criticality analysis. Extensive SPICE simulation results were reported using 45nm, 32nm and 22nm process technologies. Significant power reduction is achieved with zero or little increase in the critical path delay of the overall circuits.

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Abstract
Ⅰ. INTRODUCTION
Ⅱ. RELATED WORK
Ⅲ. DRAIN GATING TECHNIQUE AND ITS VARIATIONS
Ⅳ. THE PROPOSED LOWER-POWER DESIGN PROCEDURE AND EXPERIMENTAL RESULTS
Ⅴ. CONCLUSION
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