지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications ITC-CSCC : 2009
- 발행연도
- 2009.7
- 수록면
- 826 - 829 (4page)
이용수
초록· 키워드
오류제보하기
H.264/AVC video coding standard shows higher efficiency than previous video coding standard. One of important component for improving image quality of compressed moving pictures in H.264/AVC is deblocking filter, which is used not only for decoder but also for encoder. Deblocking filter used in encoder is called in-loop filter which was not included in previous video coding standards. This paper deals with hardware design of the deblocking filter for Hardware/Software (HW/SW) co-design of H.264/AVC. For efficient hardware design of a deblocking filter, it is very important to perform fast operations with limited hardware area resources. With small hardware resources, however, it is difficult to satisfy timing constraint. To satisfy both hardware area limitation and timing constraints, we designed compact hardware components and shared the designed components efficiently to reduce redundant hardware resources. Also, we make the efficient data processing path. In this paper, high performance architecture for the deblocking filter is proposed, and also results of the design are presented. The results show that proposed design of the deblocking filter reduces both buffer size and processing cycles by eliminating redundant buffers and memory access.
목차
Abstract
1. Introduction
2. Algorithms
3. Implementation
4. Implementation Results
5. Conclusions
Acknowledgement
References
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