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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 저널정보
- 대한전자공학회 ICEIC : International Conference on Electronics, Informations and Communications ICEIC : 2008
- 발행연도
- 2008.6
- 수록면
- 989 - 991 (3page)
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이 논문의 연구 히스토리 (4)
2008
A High-Level Power Estimation Methodology for Low Power Design
Chi-Ho Lin
ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications
2008.07
학술대회자료
A New Efficient High-Level Synthesis Methodology for Lower Power
Chi-Ho Lin
ICEIC : International Conference on Electronics, Informations and Communications
2008.06
학술대회자료
- 이 논문의 후속연구가 궁금하신가요?
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초록· 키워드
오류제보하기
This paper presents a new efficient high-level synthesis methodology for low power design.
In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, the register allocation algorithm determines the minimum register after the life-time analysis of all variable in allocat ... 전체 초록 보기
In the scheduling technique, the constraints are substituted by subgraphs, and then the number of subgraphs is minimized by using the inclusion and overlap relation efficiently. Also, the register allocation algorithm determines the minimum register after the life-time analysis of all variable in allocat ... 전체 초록 보기
목차
Abstract
1. Introduction
2. The new scheduling method for low power design
3. The low power allocation method with resource constraints
4. Experimental Result
5. Conclusion
Reference
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