Low Power Multiplier Design using Partial Product Reorder and Pass Transistor Delay Profile

Sang-Jin Hyun ,  Dong-Sun Kim ,  Tae-Ho Hwang 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2009 .07

지연 고정 루프를 이용한 저전력 고성능 Frequency Multiplier

정지완 ,  류경호 ,  정성욱

대한전자공학회 학술대회

2011 .11

A single low-voltage CMOS analog multiplier

Chaiwat sakul ,  Ittipong Chaisayun

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2007 .07

3직 Rate Multiplier의 설계 ( On the Design Methods of Ternary Rate Multiplier )

황인호 ,  심수보

한국통신학회지(정보와통신)

1981 .01

Multiplier 합성

한탁돈

대한전자공학회 기타 간행물

1992 .01

가중 인코딩 수를 이용한 직렬 십진 고정소수점 곱셈기 설계

유창헌 ,  정용수 ,  김진혁 외 1명

대한전자공학회 학술대회

2014 .06

Novel Pass-transistor Logic based Ultralow Power Variation Resilient CMOS Full Adder

Manisha Gudu ,  i ,  Aminul Islam

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2017 .04

An improved bipolar multiplier using a high linear transconductors with wideband input

Sung-Ho Yun ,  Yun-Mi Na ,  Hyeong-Woo Cha

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2008 .07

Sleep transistor sizing through a path search and power gating considering delay for reducing leakage power

Sangwoo Han ,  Joohee Choung ,  Juho Kim

ICEIC : International Conference on Electronics, Informations and Communications

2010 .06

By Pass System

이경우

시멘트

2000 .01

Lower Power Booth Multiplier

김진혁 ,  이준성 ,  조준동

대한전자공학회 학술대회

1998 .01

A POWER MINIMIZATION TECHNIQUE IN A 54 x 54 BIT MULTIPLIER

Min Kyu Song ,  Kunihi ,  o Asada

ICVC : International Conference on VLSI and CAD

1995 .01

3値 Rate Multiplier의 設計

黃仁浩 ,  沈壽輔

한국통신학회논문지

1981 .12

조립형 박막 트랜지스터 모델링 프레임워크

정태호

반도체디스플레이기술학회지

2017 .01

Transistor의 원리

이정한

대한전자공학회 기타 간행물

1965 .01

Low Power Latch-adder Based Multiplier Design

Jin-Fa Lin

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE

2017 .12

A Low-Power Booth Multiplier Using Data Partitioning

Jong Su Pa ,  k ,  Jinsang Kim 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

2003 .07

Low-Power Parallel Multiplier Using MOS Current Mode Logic Circuit

Yoon Sang Lee ,  Jeong Beom Kim

대한전자공학회 ISOCC

2007 .10

Complementary Pass-Transistor Logic 회로의 모델링 및 최적 사이징 ( The Modeling and Optimal Sizing of Complementary Pass-Transistor Logic Circuits )

이영중 ,  정항근

한국통신학회 학술대회논문집

1997 .01

Design of an 32 bit Asynchronous Multiplier

Tae Hack Lee ,  Hoon Mo Yang ,  Seung Il Sohn 외 1명

ITC-CSCC :International Technical Conference on Circuits Systems, Computers and Communications

1998 .01