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연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2006.11
- 수록면
- 419 - 422 (4page)
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초록· 키워드
오류제보하기
Due to increased integration density and reduced threshold voltages, leakage current reduction becomes important in the CMOS design for low power consumption. In a CMOS combinational logic circuit, the leakage current in the standby state depends on the state of the inputs and the number of stacked off transistors.
In this paper we present new control transistor insertion algorithm for minimal leakage power. This algorithm efficiently finds the gates for replacement and it reduces leakage current 51.72% on the average for IBM 0.18㎛ processing technology. This algorithm has proven to be very useful in reducing leakage currents in standby mode of operation.
In this paper we present new control transistor insertion algorithm for minimal leakage power. This algorithm efficiently finds the gates for replacement and it reduces leakage current 51.72% on the average for IBM 0.18㎛ processing technology. This algorithm has proven to be very useful in reducing leakage currents in standby mode of operation.
목차
Abstract
Ⅰ. 서론
Ⅱ. Control Transistor Insertion
Ⅲ. Simulation Result
Ⅳ. 결론
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