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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.12 No.3
- 발행연도
- 2012.9
- 수록면
- 360 - 369 (10page)
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초록· 키워드
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The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps (NIT). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of NIT originated by the movement of hydrogen species (h<SUP>*</SUP>) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the N<SUB>IT</SUB> generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated N<SUB>IT</SUB>.
목차
Abstract
Ⅰ. INTRODUCTION
Ⅱ. EXPERIMENTAL PROCEDURE
Ⅲ. RESULTS AND DISCUSSION
Ⅳ. CONCLUSIONS
ACKNOWLEDGMENTS
REFERENCES
참고문헌 (19)
참고문헌 신청
1. [학술지(정기간행물)] - J.-D. Lee / 2002 / Effects of Floating-Gate Interference on NAND Flash Memory Cell operation / IEEE Electron Device letters 23 (5) : 264 ~ 266
2. [학술지(정기간행물)] - Y. Wang / 2005 / An analytical retention model for SONOS nonvolatile memory devices in the excess electron state / Solid-State Elect 49 : 97 ~ 107
3. [학술대회논문] - S. D. Suk / 2005 / High Performance 5nm radius Twin Silicon Nanowire MOSFET(TSNWFET) : Fabrication on Bulk Si Wafer, Characteristics, and Reliability / Technical Digest of IEDM : 717 ~ 713
4. [학술대회논문] - K. H. Yeo / 2006 / Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15nm Length Gate and 4nm Radius Nanowires / Technical Digest of IEDM : 539 ~ 542
5. [학술대회논문] - Y. Park / 2006 / Highly Manufacturable 32Gb Multi – level NAND Flash Memory with 0.0098 μm2 Cell Size using TANOS(Si – Oxide – Al2O3 – TaN) Cell Technology / Technical Digest of IEDM
2. [학술지(정기간행물)] - Y. Wang / 2005 / An analytical retention model for SONOS nonvolatile memory devices in the excess electron state / Solid-State Elect 49 : 97 ~ 107
3. [학술대회논문] - S. D. Suk / 2005 / High Performance 5nm radius Twin Silicon Nanowire MOSFET(TSNWFET) : Fabrication on Bulk Si Wafer, Characteristics, and Reliability / Technical Digest of IEDM : 717 ~ 713
4. [학술대회논문] - K. H. Yeo / 2006 / Gate-All-Around (GAA) Twin Silicon Nanowire MOSFET (TSNWFET) with 15nm Length Gate and 4nm Radius Nanowires / Technical Digest of IEDM : 539 ~ 542
5. [학술대회논문] - Y. Park / 2006 / Highly Manufacturable 32Gb Multi – level NAND Flash Memory with 0.0098 μm2 Cell Size using TANOS(Si – Oxide – Al2O3 – TaN) Cell Technology / Technical Digest of IEDM
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