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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.14 No.2
- 발행연도
- 2014.4
- 수록면
- 139 - 145 (7page)
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초록· 키워드
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Control of threshold voltage (V<SUB>T</SUB>) by ground-plane (GP) technique for planar tunnel fieldeffect transistor (TFET) is studied for the first time using TCAD simulation method. Although GP technique appears to be similarly useful for the TFET as for the metal-oxide-semiconductor field-effect transistor (MOSFET), some unique behaviors such as the small controllability under weak ground doping and dependence on the dopant polarity are also observed. For V<SUB>T</SUB>-modulation larger than 100 mV, heavy ground doping over 1×1020 cm<SUP>-3</SUP> or back biasing scheme is preferred in case of TFETs. Polarity dependence is explained with a mechanism similar to the punch-through of MOSFETs. In spite of some minor differences, this result shows that both MOSFETs and TFETs can share common V<SUB>T</SUB>-control scheme when these devices are co-integrated.
목차
Abstract
I. INTRODUCTION
II. MODEL DEVICE AND DEFINITION OF PARAMETERS
III. RESULTS AND DISCUSSION
III. CONCLUSIONS
REFERENCES
참고문헌 (12)
참고문헌 신청
1. [학술대회논문] - A. C. Seabaugh / 2010 / Low-Voltage Tunnel Transistors for Beyond CMOS Logic / Proceedings of IEEE 98 : 2095 ~ 2110
3. [학술지(정기간행물)] - Min Jin Lee / 2011 / Dependency of Tunneling Field-Effect Transistor (TFET) Characteristics on Operation Regions / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (4) : 287 ~ 294
4. [학술지(정기간행물)] - 조성재 / 2011 / Design Optimization of a Type‐I Heterojunction Tunneling Field‐Effect Transistor (I‐HTFET) for High Performance Logic Technology / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (3) : 182 ~ 189
5. [학술대회논문] - V. Tiwari / 1998 / Reducing Power in Highperformance Microprocessors / Proc. ACM/IEEE Design Automation Conference : 732 ~ 737
6. [학술대회논문] - L. Wei / 2000 / Low voltage low power CMOS design techniques for deep submicron ICs / Proc. Intl. Conference on VLSI Design : 24 ~ 29
3. [학술지(정기간행물)] - Min Jin Lee / 2011 / Dependency of Tunneling Field-Effect Transistor (TFET) Characteristics on Operation Regions / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (4) : 287 ~ 294
4. [학술지(정기간행물)] - 조성재 / 2011 / Design Optimization of a Type‐I Heterojunction Tunneling Field‐Effect Transistor (I‐HTFET) for High Performance Logic Technology / JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 11 (3) : 182 ~ 189
5. [학술대회논문] - V. Tiwari / 1998 / Reducing Power in Highperformance Microprocessors / Proc. ACM/IEEE Design Automation Conference : 732 ~ 737
6. [학술대회논문] - L. Wei / 2000 / Low voltage low power CMOS design techniques for deep submicron ICs / Proc. Intl. Conference on VLSI Design : 24 ~ 29
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