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학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
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논문 기본 정보
- 자료유형
- 학술대회자료
- 저자정보
- 발행연도
- 2006.11
- 수록면
- 950 - 953 (4page)
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초록· 키워드
오류제보하기
Most digital signal processing (DSP) algorithms for multimedia and communication applications require multiplication and addition operations. Especially matrix-matrix or matrix-vector the multiplications frequently used in DSP implementations needs inner product arithmetic which takes the most processing time. Also multiplications for the DSP algorithms for software defined radio (SDR) applications require different input bitwidths. Therefore, the multiplications for inner product need to be sufficiently flexible in terms of bitwidths to utilize hardware resources efficiently. This paper proposes a novel reconfigurable inner product architecture based on a pipelined adder array, which offers increased flexibility in bitwidths of input arrays. The proposed architecture consists of sixteen 4×4 multipliers and a pipelined adder array and can compute the inner product of input arrays with any combination of multiples of 4 bitwidths such as 4×4, 4×8, 4×12, ... 16×16. Experimental results show that the proposed architecture has latency of maximum 9 clock cycles and throughput of 1 clock cycle for inner product of various bitwidths of input arrays. When TSMC 0.18 ㎛ libraries are used, the chip area and critical path of the proposed architecture are 12,613.7 gates and 2.1㎱, respectively. The proposed architecture can be applied to a reconfigurable arithmetic engine for real-time SDR system designs.
목차
Abstract
Ⅰ. 서론
Ⅱ. 본론
Ⅲ. 제안된 구조의 하드웨어 구성 예
Ⅳ. 실험 결과
Ⅴ. 결론
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