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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.2
- 발행연도
- 2016.4
- 수록면
- 159 - 165 (7page)
이용수
초록· 키워드
오류제보하기
Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.
목차
Abstract
I. INTRODUCTION
II. SIMULATION APPROACH
III. RESULTS AND DISCUSSION
IV. CONCLUSION
REFERENCES
참고문헌 (14)
참고문헌 신청
O. Kononchuk and B.-Y. Nguyen, Silicon-On- Insulator (SOI) Technology: Manufacture and Applications, Woodhead Publishing, Cambridge, UK, 2014.
G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,” J. Appl. Phys., vol. 93, no. 9, pp. 4955 - 4978, May 2013.
M. Wu, X. Jin, H.-I. Kwon, R. Chuai, X. Liu, and J.-H. Lee, “The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling,“ J. Semicond. Technol. Sci., vol. 13, no. 3, pp. 245 - 251, Jun. 2013.
H. Nam, G. S. Lee, H. Lee, I. J. Park, and C. Shin, “Analysis of Random Variations and Variation- Robust Advanced Device Structures,” J. Semicond. Technol. Sci., vol. 14, no. 1, pp. 8 - 22, Feb. 2014.
S. Y. Kim, J. H. Seo, Y. J. Yoon, G. M. Yoo, Y. J. Kim, H. R. Eun, H. S. Kang, J. Kim, S. Cho, J.-H. Lee, and I. M. Kang, “Design and Analysis of Sub- 10 nm Junctionless Fin-Shaped Field-Effect Transistors,” J. Semicond. Technol. Sci., vol. 14, no. 5, pp. 508 - 517, Oct. 2014.
G. K. Celler and S. Cristoloveanu, “Frontiers of silicon-on-insulator,” J. Appl. Phys., vol. 93, no. 9, pp. 4955 - 4978, May 2013.
M. Wu, X. Jin, H.-I. Kwon, R. Chuai, X. Liu, and J.-H. Lee, “The Optimal Design of Junctionless Transistors with Double-Gate Structure for reducing the Effect of Band-to-Band Tunneling,“ J. Semicond. Technol. Sci., vol. 13, no. 3, pp. 245 - 251, Jun. 2013.
H. Nam, G. S. Lee, H. Lee, I. J. Park, and C. Shin, “Analysis of Random Variations and Variation- Robust Advanced Device Structures,” J. Semicond. Technol. Sci., vol. 14, no. 1, pp. 8 - 22, Feb. 2014.
S. Y. Kim, J. H. Seo, Y. J. Yoon, G. M. Yoo, Y. J. Kim, H. R. Eun, H. S. Kang, J. Kim, S. Cho, J.-H. Lee, and I. M. Kang, “Design and Analysis of Sub- 10 nm Junctionless Fin-Shaped Field-Effect Transistors,” J. Semicond. Technol. Sci., vol. 14, no. 5, pp. 508 - 517, Oct. 2014.
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