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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.16 No.3
- 발행연도
- 2016.6
- 수록면
- 319 - 329 (11page)
이용수
초록· 키워드
오류제보하기
High-level design aids are mandatory for design of a continuous-time delta-sigma modulator (CTDSM). This paper proposes a top-down methodology design to generate a noise transfer function (NTF) which is compensated for excess loop delay (ELD). This method is applicable to low pass loop-filter topologies. Non-ideal effects including ELD, integrator scaling issue, finite op-amp performance, clock jitter and DAC inaccuracies are explicitly represented in a behavioral simulation of a CTDSM. Mathematical modeling using MATLAB is supplemented with circuit-level simulation using Verilog-A blocks. Behavioral simulation and circuit-level simulation using Verilog-A blocks are used to validate our approach.
목차
Abstract
I. INTRODUCTION
II. SD TOOLBOX DESIGN FLOW
III. PROPOSED DESIGN FLOW
IV. BEHAVIORAL MODELING
V. CONCLUSION
REFERENCES
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UCI(KEPA) : I410-ECN-0101-2017-569-000775438