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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.22 No.4
- 발행연도
- 2022.8
- 수록면
- 259 - 265 (7page)
- DOI
- 10.5573/JSTS.2022.22.4.259
이용수
초록· 키워드
오류제보하기
This paper presents a 3<SUP>rd</SUP>-order time-domain continuous-time delta-sigma modulator (CTDSM) using two voltage-controlled oscillator (VCO)-based integrators and a gated ring oscillator (GRO)-based quantizer. The GRO-based quantizer has 1<SUP>st</SUP>-order noise-shaping characteristics without the increase of the signal transfer function (STF) order and has magnificent linearity. Also, the output of the GRO-based quantizer has an intrinsic data weighted averaging (DWA)-based dynamic element matching (DEM) pattern that is less susceptible to the DAC mismatch. The PWM signal, which is the input of the GRO-based quantizer, is generated by the VCO-based integrator without additional blocks. In the pre-layout simulation, the CTDSM consumes 3.84 mW and achieves an SNDR of 71.2 dB at a 400-MSs sampling frequency and a 10-MHz bandwidth.
목차
Abstract
I. INTRODUCTION
II. REVIEW OF THE TIME-DOMAIN QUANTIZERS
III. ARCHITECTURE OF CTDSM
IV. CIRCUIT IMPLEMENTATIONS
V. SIMULATION RESULTS
VI. CONCLUSIONS
REFERENCES
참고문헌 (11)
참고문헌 신청
K. Lee, Y. Yoon, and N. Sun, “A 10MHz-BW, 5.6mW, 70dB SNDR ΔΣ ADC Using VCO-Based Integrators with Intrinsic DEM,” 2013 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2006-2009, May, 2013.
M. Z. Straayer and M. H. Perrott, “A 10-bit 20MHz 38mW 950MHz CT ΔΣ ADC with a 5-bit noiseshaping VCO-based quantizer and DEM circuit in 0.13u cmos,” 2007 IEEE Symposium on VLSI Circuits, pp. 246-247, Jun., 2007.
M. Park and M. H. Perrott, “A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 12, pp. 3344-3358, Dec., 2009.
K. Lee, Y. Yoon, and N. Sun, “A Scaling-Friendly Low-Power Small-Area ΔΣ ADC With VCOBased Integrator and Intrinsic Mismatch Shaping Capability,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 5, No. 4, pp. 561-573, Dec., 2007.
S. Pavan, “Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems-II, Vol. 55, No. 11, pp. 1119-1123, Nov., 2008.
M. Z. Straayer and M. H. Perrott, “A 10-bit 20MHz 38mW 950MHz CT ΔΣ ADC with a 5-bit noiseshaping VCO-based quantizer and DEM circuit in 0.13u cmos,” 2007 IEEE Symposium on VLSI Circuits, pp. 246-247, Jun., 2007.
M. Park and M. H. Perrott, “A 78 dB SNDR 87 mW 20 MHz Bandwidth Continuous-Time ΔΣ ADC With VCO-Based Integrator and Quantizer Implemented in 0.13 μm CMOS,” IEEE Journal of Solid-State Circuits, Vol. 44, No. 12, pp. 3344-3358, Dec., 2009.
K. Lee, Y. Yoon, and N. Sun, “A Scaling-Friendly Low-Power Small-Area ΔΣ ADC With VCOBased Integrator and Intrinsic Mismatch Shaping Capability,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 5, No. 4, pp. 561-573, Dec., 2007.
S. Pavan, “Excess Loop Delay Compensation in Continuous-Time Delta-Sigma Modulators,” IEEE Transactions on Circuits and Systems-II, Vol. 55, No. 11, pp. 1119-1123, Nov., 2008.
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