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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 발행연도
- 2018.10
- 수록면
- 1 - 9 (9page)
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초록· 키워드
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Modern graphics processing units (GPUs) have become one of the most attractive platforms in exploiting high thread level parallelism with the support of new programming tools such as CUDA and OpenCL. Recent GPUs has applied cache hierarchy to support irregular memory access patterns; however, L1 data cache (L1D) exhibits poor efficiency in the GPU. This paper shows that the L1D does not always positively affect the applications in terms of performance and energy efficiency for the GPU. The performance of the GPU is even harmed by using the L1D for lots of applications. Our proposed technique exploits the characteristics of the currently-executed applications to predict the performance impact of the L1D on the GPU and then decides whether to continuously use the cache for the application or not. Our experimental results show that the proposed technique improves the GPU performance by 9.4% and saves up to 52.1% of the power consumption in the L1D.
목차
Abstract
I. Introduction
II. Related Work
III. Background
IV. Experiments
V. Conclusions
REFERENCES
참고문헌 (28)
참고문헌 신청
W. Jia / 2014 / MRPB: Memory Request Prioritization for Massively Parallel Processors / IEEE International Symposium on High Performance Computer Architecture (HPCA) :272~283
NVIDIA / 2009 / Whitepaper: NVIDIA's Next Generation CUDA Compute and Graphics Architecture
Y. Torres. / 2011 / Understanding the Impact of CUDA Tuning Techniques for Fermi / High Performance Computing and Simulation (HPCS) :631~639
A. Jog / 2013 / OWL: Cooperative Thread Array Aware Scheduling Techniques for Improving GPGPU Performance / International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) :395~406
S. Lee / 2015 / CAWA: Coordinated Warp Scheduling and Cache Prioritization for Critical Warp Acceleration of GPGPU Workloads / the International Symposium on Computer Architecture (ISCA) :515~527
NVIDIA / 2009 / Whitepaper: NVIDIA's Next Generation CUDA Compute and Graphics Architecture
Y. Torres. / 2011 / Understanding the Impact of CUDA Tuning Techniques for Fermi / High Performance Computing and Simulation (HPCS) :631~639
A. Jog / 2013 / OWL: Cooperative Thread Array Aware Scheduling Techniques for Improving GPGPU Performance / International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) :395~406
S. Lee / 2015 / CAWA: Coordinated Warp Scheduling and Cache Prioritization for Critical Warp Acceleration of GPGPU Workloads / the International Symposium on Computer Architecture (ISCA) :515~527
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UCI(KEPA) : I410-ECN-0101-2019-004-000122271