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논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- 대한전자공학회 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE Journal of Semiconductor Technology and Science Vol.19 No.3
- 발행연도
- 2019.6
- 수록면
- 292 - 299 (8page)
- DOI
- 10.5573/JSTS.2019.19.3.292
이용수
초록· 키워드
오류제보하기
This paper proposes a 1.5-GHz ring oscillator-based dual-loop phase locked loop (PLL) with a frequency-to-voltage converter (FVC). By forming an additional high bandwidth path in the conventional PLL with the FVC, the proposed dual-loop PLL can effectively suppress the voltage controlled oscillator (VCO) noise and reference noise. Tested with an arbitrary power supply noise injection, the phase noise of the proposed PLL with FVC was -88.6 dBc/Hz at a 1-MHz offset, while that of the conventional PLL was -78.4 dBc/Hz. The measured reference spur was also reduced from -38.7 dBc to -59.3 dBc. The proposed dual-loop PLL was fabricated in a 28-nm CMOS process. It occupies an area of 0.23 ㎟ and consumes 4 mW from a 1.0-V power supply when it operates at 1.5-GHz.
목차
Abstract
I. INTRODUCTION
II. PROPOSED ARCHITECTURE
III. ANALYSIS OF THE PROPOSED PLL
IV. MEASUREMENT RESULTS
V. CONCLUSIONS
REFERENCES
참고문헌 (6)
참고문헌 신청
Jri Lee, Huaide Wang, “Study of Subharmonically Injection-Locked PLLs,” IEEE Journal of Solid- State Circuits, vol. 44, no. 5, pp. 1539-1553, May 2009.
Sheng Ye, Lars Jansson, and Ian Galton, “A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, pp. 1795-1830, Dec. 2002.
Yi-Chieh Huang, Shen-Iuan Liu, “A 2.4GHz subharmonically injection-locked PLL with selfcalibrated injection timing,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 338-340, Feb. 2012.
Werner Grollitsch, Roberto Nonis, “A fractional-N, all-digital injetion-locked PLL with wide tuning range digitally controlled ring oscillator and Bang- Bang phase detection for temperature tracking in 40nm CMOS,” in European Solid-State Circuits Conference (ESSCIRC), pp. 201-204, Sept. 2016.
Young-Shig Choi, “A Negative Feedback Looped Voltage-Controlled Ring Oscillator With Frequency Voltage Converter,” IEEE Transactions on Microwave Theory and Techniques, Vol. 61, No. 9, pp. 3271-3276, Sept. 2013.
Sheng Ye, Lars Jansson, and Ian Galton, “A Multiple-Crystal Interface PLL With VCO Realignment to Reduce Phase Noise,” IEEE Journal of Solid-State Circuits, Vol. 37, No. 12, pp. 1795-1830, Dec. 2002.
Yi-Chieh Huang, Shen-Iuan Liu, “A 2.4GHz subharmonically injection-locked PLL with selfcalibrated injection timing,” in Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 338-340, Feb. 2012.
Werner Grollitsch, Roberto Nonis, “A fractional-N, all-digital injetion-locked PLL with wide tuning range digitally controlled ring oscillator and Bang- Bang phase detection for temperature tracking in 40nm CMOS,” in European Solid-State Circuits Conference (ESSCIRC), pp. 201-204, Sept. 2016.
Young-Shig Choi, “A Negative Feedback Looped Voltage-Controlled Ring Oscillator With Frequency Voltage Converter,” IEEE Transactions on Microwave Theory and Techniques, Vol. 61, No. 9, pp. 3271-3276, Sept. 2013.
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