지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
이용수
Abstract
Ⅰ. 서론
Ⅱ. 전통적인 구조의 PLL
Ⅲ. 전력 절감 기술을 이용한 PLL
Ⅳ. 시뮬레이션 결과 및 결론
참고문헌
논문 유사도에 따라 DBpia 가 추천하는 논문입니다. 함께 보면 좋을 연관 논문을 확인해보세요!
A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions
전력전자학회 학술대회 논문집
2017 .11
실시간 시뮬레이션 시스템을 이용한 PLL 설계
Proceedings of KIIT Conference
2018 .06
위상 고정 루프 (Phase Locked Loop)의 모델링
대한전자공학회 학술대회
2018 .06
CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies
Journal of Electromagnetic Engineering And Science
2017 .04
Benchmarking of Small-signal Dynamics of single-phase PLLs
ICPE(ISPE)논문집
2015 .06
Performance Analysis of Three-Phase Phase-Locked Loops for Distorted and Unbalanced Grids
JOURNAL OF POWER ELECTRONICS
2017 .01
IoT 어플리케이션을 위한 초저전력 PLL 설계
대한전자공학회 학술대회
2021 .06
Study on Low-jitter and Low-power PLL Architectures for Mobile Audio Systems
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2022 .12
A Method to Improve the Performance of Phase-Locked Loop (PLL) for a Single-Phase Inverter Under the Non-Sinusoidal Grid Voltage Conditions
전력전자학회논문지
2018 .08
Double-PLL을 이용한 홀 센서 기반 PMSM 제어의 위치 추정 성능 개선
전력전자학회논문지
2017 .06
Design of a High-performance High-pass Generalized Integrator Based Single-phase PLL
JOURNAL OF POWER ELECTRONICS
2017 .09
12.2 GHz All-digital PLL with Pattern Memorizing Cells for Low Power/low Jitter using 65 nm CMOS Process
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2021 .04
능동필터를 이용한 빠른 Lock Time을 갖는 PLL
전자공학회논문지
2018 .10
Dynamics Assessment of Grid-Synchronization Algorithms for Single-Phase Grid-Connected Converters
ICPE(ISPE)논문집
2015 .06
New Configuration of a PLDRO with an Interconnected Dual PLL Structure for K-Band Application
Journal of Electromagnetic Engineering And Science
2017 .07
Type-3 PLL Based Speed Estimation Scheme for Sensorless Linear Induction Motor Drives
ICPE(ISPE)논문집
2019 .05
빠른 Lock Time을 가진 Switched Capacitor 위상고정루프의 수식적 분석
대한전자공학회 학술대회
2017 .06
Performance Evaluations of Four MAF-Based PLL Algorithms for Grid-Synchronization of Three-Phase Grid-Connected PWM Inverters and DGs
JOURNAL OF POWER ELECTRONICS
2016 .09
A Hybrid Filtering Stage Based Quasi-type-1 PLL under Distorted Grid Conditions
JOURNAL OF POWER ELECTRONICS
2017 .05
A 1.25 GHz Low Power Multi-phase PLL Using Phase Interpolation between Two Complementary Clocks
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE
2015 .12
0